KRUSH Labs | R&D center and Laboratory

FPGA Design Engineer

Mid to Senior Level

R&D Department

High Tech Campus Eindhoven

Mon – Fri (4d/week onsite)

Reporting to Lead RF Engineer

Job summary

Our company is developing a cutting-edge wireless communication system to connect multiple portable devices. Long range, high data rates, low latency, resistance to interferences, and multipath make this problem particularly challenging, giving the candidate unique opportunities to research, design, and implement the next-generation radio communication systems.

What you’ll be doing

KRUSH Labs

What you’ll be doing

KRUSH Labs

What you’ll be doing

KRUSH Labs

What you’ll be doing

Key responsibilities

Design, simulate, and measure manufactured RF chains and device assemblies.
Select key RF components such as FEMs, filters, and switches.
Create and optimize RF board layouts and troubleshoot related issues.
Collaborate closely with software and hardware development teams to meet system-wide requirements.

Design, simulate, and measure manufactured RF chains and device assemblies.
Select key RF components such as FEMs, filters, and switches.
Create and optimize RF board layouts and troubleshoot related issues.
Collaborate closely with software and hardware development teams to meet system-wide requirements.

Design, simulate, and measure manufactured RF chains and device assemblies.
Select key RF components such as FEMs, filters, and switches.
Create and optimize RF board layouts and troubleshoot related issues.
Collaborate closely with software and hardware development teams to meet system-wide requirements.

Design, simulate, and measure manufactured RF chains and device assemblies.
Select key RF components such as FEMs, filters, and switches.
Create and optimize RF board layouts and troubleshoot related issues.
Collaborate closely with software and hardware development teams to meet system-wide requirements.

What you should know

KRUSH Labs

What you should know

KRUSH Labs

What you should know

KRUSH Labs

What you should know

Tech qualifications

5+ years of experience in FPGA or VLSI (FrontEnd) design.
Strong Verilog/SystemVerilog skills (SystemVerilog preferred).
Intermediate-level proficiency in C/C++.
Experience with lint-clean RTL development and structured code practices.
Solid understanding of SDC constraints and static timing analysis.
Familiarity with clock domain crossing (CDC), reset domain crossing (RDC), and low-power design methodologies.
Experience with wireless communication technologies and signal processing concepts, such as MIMO and OFDM.
Awareness of verification concepts and methodologies, e.g., UVM.
Experience implementing fixed-point DSP algorithms in RTL is a strong plus.

5+ years of experience in FPGA or VLSI (FrontEnd) design.
Strong Verilog/SystemVerilog skills (SystemVerilog preferred).
Intermediate-level proficiency in C/C++.
Experience with lint-clean RTL development and structured code practices.
Solid understanding of SDC constraints and static timing analysis.
Familiarity with clock domain crossing (CDC), reset domain crossing (RDC), and low-power design methodologies.
Experience with wireless communication technologies and signal processing concepts, such as MIMO and OFDM.
Awareness of verification concepts and methodologies, e.g., UVM.
Experience implementing fixed-point DSP algorithms in RTL is a strong plus.

5+ years of experience in FPGA or VLSI (FrontEnd) design.
Strong Verilog/SystemVerilog skills (SystemVerilog preferred).
Intermediate-level proficiency in C/C++.
Experience with lint-clean RTL development and structured code practices.
Solid understanding of SDC constraints and static timing analysis.
Familiarity with clock domain crossing (CDC), reset domain crossing (RDC), and low-power design methodologies.
Experience with wireless communication technologies and signal processing concepts, such as MIMO and OFDM.
Awareness of verification concepts and methodologies, e.g., UVM.
Experience implementing fixed-point DSP algorithms in RTL is a strong plus.

5+ years of experience in FPGA or VLSI (FrontEnd) design.
Strong Verilog/SystemVerilog skills (SystemVerilog preferred).
Intermediate-level proficiency in C/C++.
Experience with lint-clean RTL development and structured code practices.
Solid understanding of SDC constraints and static timing analysis.
Familiarity with clock domain crossing (CDC), reset domain crossing (RDC), and low-power design methodologies.
Experience with wireless communication technologies and signal processing concepts, such as MIMO and OFDM.
Awareness of verification concepts and methodologies, e.g., UVM.
Experience implementing fixed-point DSP algorithms in RTL is a strong plus.

What helps you thrive here

KRUSH Labs

What helps you thrive here

KRUSH Labs

What helps you thrive here

KRUSH Labs

What helps you thrive here

Skills & abilities

Strong analytical and problem-solving mindset with a detail-oriented approach.
Effective communication skills and the ability to work across multidisciplinary teams.
Willingness to learn and adapt to new challenges and evolving technologies.
Commitment to quality, innovation, and high-performance design.

Strong analytical and problem-solving mindset with a detail-oriented approach.
Effective communication skills and the ability to work across multidisciplinary teams.
Willingness to learn and adapt to new challenges and evolving technologies.
Commitment to quality, innovation, and high-performance design.

Strong analytical and problem-solving mindset with a detail-oriented approach.
Effective communication skills and the ability to work across multidisciplinary teams.
Willingness to learn and adapt to new challenges and evolving technologies.
Commitment to quality, innovation, and high-performance design.

Strong analytical and problem-solving mindset with a detail-oriented approach.
Effective communication skills and the ability to work across multidisciplinary teams.
Willingness to learn and adapt to new challenges and evolving technologies.
Commitment to quality, innovation, and high-performance design.

Why joining us?

Krush Labs

Why joining us?

Krush Labs

Why joining us?

Krush Labs

Why joining us?

This is a chance to join the team at the ground floor of something big! Here’s why we think you’ll love it:

No bureaucracy – we move fast to make an impact

True ownership – you shape the team & culture from day one

Freedom to innovate – your ideas, your way

Work with brilliant minds – collaborate with international PhD scientists & researchers

No bureaucracy – we move fast to make an impact

True ownership – you shape the team & culture from day one

Freedom to innovate – your ideas, your way

Work with brilliant minds – collaborate with international PhD scientists & researchers

No bureaucracy – we move fast to make an impact

True ownership – you shape the team & culture from day one

Freedom to innovate – your ideas, your way

Work with brilliant minds – collaborate with international PhD scientists & researchers

No bureaucracy – we move fast to make an impact

True ownership – you shape the team & culture from day one

Freedom to innovate – your ideas, your way

Work with brilliant minds – collaborate with international PhD scientists & researchers

Let’s build the future together

KRUSH Labs

Let’s build the future together

KRUSH Labs

Let’s build the future together

KRUSH Labs

Let’s build the future together

Apply form

Join the team — tell us about your background and motivation.

FPGA Design Engineer

FPGA Design Engineer

FPGA Design Engineer

FPGA Design Engineer

Job summary

Job summary

Job summary

Job summary

Key responsibilities

Key responsibilities

Key responsibilities

Key responsibilities

Design, simulate, and measure manufactured RF chains and device assemblies.

Select key RF components such as FEMs, filters, and switches.

Create and optimize RF board layouts and troubleshoot related issues.

Collaborate closely with software and hardware development teams to meet system-wide requirements.

Design, simulate, and measure manufactured RF chains and device assemblies.

Select key RF components such as FEMs, filters, and switches.

Create and optimize RF board layouts and troubleshoot related issues.

Collaborate closely with software and hardware development teams to meet system-wide requirements.

Design, simulate, and measure manufactured RF chains and device assemblies.

Select key RF components such as FEMs, filters, and switches.

Create and optimize RF board layouts and troubleshoot related issues.

Collaborate closely with software and hardware development teams to meet system-wide requirements.

Design, simulate, and measure manufactured RF chains and device assemblies.

Select key RF components such as FEMs, filters, and switches.

Create and optimize RF board layouts and troubleshoot related issues.

Collaborate closely with software and hardware development teams to meet system-wide requirements.

Tech qualifications

Tech qualifications

Tech qualifications

Tech qualifications

5+ years of experience in FPGA or VLSI (FrontEnd) design.

Strong Verilog/SystemVerilog skills (SystemVerilog preferred).

Intermediate-level proficiency in C/C++.

Experience with lint-clean RTL development and structured code practices.

Solid understanding of SDC constraints and static timing analysis.

Familiarity with clock domain crossing (CDC), reset domain crossing (RDC), and low-power design methodologies.

Experience with wireless communication technologies and signal processing concepts, such as MIMO and OFDM.

Awareness of verification concepts and methodologies, e.g., UVM.

Experience implementing fixed-point DSP algorithms in RTL is a strong plus.

5+ years of experience in FPGA or VLSI (FrontEnd) design.

Strong Verilog/SystemVerilog skills (SystemVerilog preferred).

Intermediate-level proficiency in C/C++.

Experience with lint-clean RTL development and structured code practices.

Solid understanding of SDC constraints and static timing analysis.

Familiarity with clock domain crossing (CDC), reset domain crossing (RDC), and low-power design methodologies.

Experience with wireless communication technologies and signal processing concepts, such as MIMO and OFDM.

Awareness of verification concepts and methodologies, e.g., UVM.

Experience implementing fixed-point DSP algorithms in RTL is a strong plus.

5+ years of experience in FPGA or VLSI (FrontEnd) design.

Strong Verilog/SystemVerilog skills (SystemVerilog preferred).

Intermediate-level proficiency in C/C++.

Experience with lint-clean RTL development and structured code practices.

Solid understanding of SDC constraints and static timing analysis.

Familiarity with clock domain crossing (CDC), reset domain crossing (RDC), and low-power design methodologies.

Experience with wireless communication technologies and signal processing concepts, such as MIMO and OFDM.

Awareness of verification concepts and methodologies, e.g., UVM.

Experience implementing fixed-point DSP algorithms in RTL is a strong plus.

5+ years of experience in FPGA or VLSI (FrontEnd) design.

Strong Verilog/SystemVerilog skills (SystemVerilog preferred).

Intermediate-level proficiency in C/C++.

Experience with lint-clean RTL development and structured code practices.

Solid understanding of SDC constraints and static timing analysis.

Familiarity with clock domain crossing (CDC), reset domain crossing (RDC), and low-power design methodologies.

Experience with wireless communication technologies and signal processing concepts, such as MIMO and OFDM.

Awareness of verification concepts and methodologies, e.g., UVM.

Experience implementing fixed-point DSP algorithms in RTL is a strong plus.

Skills & abilities

Skills & abilities

Skills & abilities

Skills & abilities

Strong analytical and problem-solving mindset with a detail-oriented approach.

Effective communication skills and the ability to work across multidisciplinary teams.

Willingness to learn and adapt to new challenges and evolving technologies.

Commitment to quality, innovation, and high-performance design.

Strong analytical and problem-solving mindset with a detail-oriented approach.

Effective communication skills and the ability to work across multidisciplinary teams.

Willingness to learn and adapt to new challenges and evolving technologies.

Commitment to quality, innovation, and high-performance design.